Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster

摘要

Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM hasdeveloped a full wafer redistribution and embedding technology as base for alarge-scale neuromorphic hardware system. The paper will give an overview ofthe neuromorphic computing platform at the KIP and the associated hardwarerequirements which drove the described technological developments. In the firstphase of the project standard redistribution technologies from wafer levelpackaging were adapted to enable a high density reticle-to-reticle routing on200mm CMOS wafers. Neighboring reticles were interconnected across the scribelines with an 8{\mu}m pitch routing based on semi-additive coppermetallization. Passivation by photo sensitive benzocyclobutene was used toenable a second intra-reticle routing layer. Final IO pads with flash gold weregenerated on top of each reticle. With that concept neuromorphic systems basedon full wafers could be assembled and tested. The fabricated high densityinter-reticle routing revealed a very high yield of larger than 99.9%. In orderto allow an upscaling of the system size to a large number of wafers withfeasible effort a full wafer embedding concept for printed circuit boards wasdeveloped and proven in the second phase of the project. The wafers werethinned to 250{\mu}m and laminated with additional prepreg layers and copperfoils into a core material. After lamination of the PCB panel the reticle IOsof the embedded wafer were accessed by micro via drilling, copperelectroplating, lithography and subtractive etching of the PCB wiringstructure. The created wiring with 50um line width enabled an access of thereticle IOs on the embedded wafer as well as a board level routing. The panelswith the embedded wafers were subsequently stressed with up to 1000 thermalcycles between 0C and 100C and have shown no severe failure formation over thecycle time.